It is not easy to design the timing considering a time gap after the rising edge of the reset signal is detected before the frequency divider starts its operation. It is difficult to predict this difference to make a design for restraining the timing gap in the reset signal.Įach parallel-serial converter performs parallel-serial conversion based on a clock signal obtained by dividing the frequency of a reference high-speed clock signal by a frequency divider. Further, the rise time of the reset signal differs depending on each parallel-serial converter in the same chip, due to the influence of manufacturing process, power-supply voltage, junction temperature, etc. Accordingly, the load capacity of the reset signal becomes large, which lengthens the rise time of the reset signal. However, since the reset signal is used also in the components other than the parallel-serial converter circuit, the reset signal path to be routed often becomes long. In such a parallel-serial converter circuit, it is general to start parallel-serial conversion after supplying a reset signal to each parallel-serial converter to reset each parallel-serial converter, to synchronize the parallel-serial converters and eliminate a timing gap therebetween. In this case, a plurality of parallel-serial converters are provided in the parallel-serial converter circuit.
![parallel to serial converter circuit parallel to serial converter circuit](http://larvierinehart.com/serial/serialadc/seriaadc.gif)
Accordingly, the high-capacity recording device has a parallel-serial converter circuit.Īs a measure for improving data transfer speed, a plurality of types of parallel data may be simultaneously converted into serial data to transmit these serial data in synchronization with each other.
![parallel to serial converter circuit parallel to serial converter circuit](https://i0.wp.com/electricalfundablog.com/wp-content/uploads/2020/01/SIPO_thumb.png)
In a high-capacity recording device such as SSD (Solid State Disk) and HDD (Hard Disk Drive), it is general that parallel data read from a recording region is converted into serial data before being transmitted. FIELDĮmbodiments of the present invention relate to a parallel-serial converter circuit. 16, 2014, the entire contents of which are incorporated herein by reference.
![parallel to serial converter circuit parallel to serial converter circuit](https://www.allaboutcircuits.com/uploads/articles/serial-in-parallel-out-shift-register-details-1.jpg)
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.